1. Field of the Invention
The present invention relates to a simulation method, a simulation program, and a semiconductor device manufacturing method. In particular, the present invention relates to a technique of simulating semiconductor device processes employing to boundary conditions.
2. Description of the Related Art
A simulation of the manufacturing processes or electric characteristics of a semiconductor device is usually restricted by various conditions such as a computation time and a computer memory capacity. To comply with the restrictions, the simulation is carried out by setting a finite calculation area. Especially, a simulation involving three-dimensional calculations needs a larger memory capacity and a longer computation elapse time than a simulation involving two-dimensional calculations, and therefore, is usually allocated with a narrow calculation area. Setting a finite calculation area for a simulation is achieved by setting boundary conditions on the boundary of the finite calculation area.
The boundary conditions influence a simulation result. This influence of the boundary conditions is often overlooked by a design engineer, and the design engineer is frequently unaware of a deviation in a simulation result from a true result to be derived from the simulation on the calculation area. When relatively simple boundary conditions such as mirror, fixed, or periodic boundary conditions are improper for a given simulation, it is difficult to choose proper boundary conditions for the simulation. If improper boundary conditions are set for the simulation, an unintended simulation result will be obtained. If the unintended simulation result is passed unnoticed to design a semiconductor device, it leads to a failure of the semiconductor device.